View SST39LF010-45-4C-B3HE_4862039.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories
Data Sheet
FEATURES:
* Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 * Single Voltage Read and Write Operations - 3.0-3.6V for SST39LF512/010/020/040 - 2.7-3.6V for SST39VF512/010/020/040 * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption (typical values at 14 MHz) - Active Current: 5 mA (typical) - Standby Current: 1 A (typical) * Sector-Erase Capability - Uniform 4 KByte sectors * Fast Read Access Time: - 45 ns for SST39LF512/010/020/040 - 55 ns for SST39LF020/040 - 70 ns for SST39VF512/010/020/040 * Latched Address and Data * Fast Erase and Byte-Program: - Sector-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Byte-Program Time: 14 s (typical) - Chip Rewrite Time: 1 second (typical) for SST39LF/VF512 2 seconds (typical) for SST39LF/VF010 4 seconds (typical) for SST39LF/VF020 8 seconds (typical) for SST39LF/VF040 * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm) - 48-ball TFBGA (6mm x 8mm) - 34-ball WFBGA (4mm x 6mm) for 1M and 2M * All devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39LF512, SST39LF010, SST39LF020, SST39LF040 and SST39VF512, SST39VF010, SST39VF020, SST39VF040 are 64K x8, 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF512/010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF512/010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39LF512/010/020/040 and SST39VF512/010/020/ 040 devices provide a maximum Byte-Program time of 20 sec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, they are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices are suited for applications that require convenient and economical updating of program, configu(c)2010 Silicon Storage Technology, Inc. S71150-14-000 01/10 1
ration, or data memory. For all system applications, they significantly improves performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet surface mount requirements, the SST39LF512/ 010/020/040 and SST39VF512/010/020/040 devices are offered in 32-lead PLCC and 32-lead TSOP packages. The SST39LF/VF010 and SST39LF/VF020 are also offered in a 48-ball TFBGA package. See Figures 2, 3, 4, and 5 for pin assignments.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 11 for timing waveforms. Any commands written during the Sector-Erase operation will be ignored.
Chip-Erase Operation
The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the `1's state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 12 for timing diagram, and Figure 20 for the flowchart. Any commands written during the ChipErase operation will be ignored.
Read
The Read operation of the SST39LF512/010/020/040 and SST39VF512/010/020/040 device is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6).
Byte-Program Operation
The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 are programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 s. See Figures 7 and 8 for WE# and CE# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.
Write Operation Status Detection
The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
2
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Data# Polling (DQ7)
When the SST39LF512/010/020/040 and SST39VF512/ 010/020/040 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a "0". Once the internal Erase operation is completed, DQ7 will produce a "1". The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 18 for a flowchart.
Software Data Protection (SDP)
The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 provide the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC.
Product Identification
The Product Identification mode identifies the devices as the SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 and SST39LF/VF040 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 13 for the Software ID Entry and Read timing diagram, and Figure 19 for the Software ID entry command sequence flowchart. TABLE 1: Product Identification
Address Manufacturer's ID Device ID SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 0001H 0001H 0001H 0001H D4H D5H D6H D7H
T1.1 1150
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `0's and `1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 10 for Toggle Bit timing diagram and Figure 18 for a flowchart.
Data BFH
Data Protection
The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes.
0000H
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 14 for timing waveform, and Figure 19 for a flowchart.
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
3
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
X-Decoder
SuperFlash Memory
Memory Address
Address Buffers & Latches Y-Decoder CE#
OE# WE#
Control Logic
I/O Buffers and Data Latches DQ7 - DQ0
1150 B1.1
FIGURE 1: Functional Block Diagram
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
WE# WE# WE# WE#
VDD
A12
A15
A16
A18
VDD
A12
A15
A16
VDD
A12
A15
A16
NC
VDD
A12
A15
NC
NC
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
NC
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
5 6 7 8 9 10 11 12 13
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512
4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
NC
A17
NC
A17
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
32-lead PLCC Top View
21 14 15 16 17 18 19 20
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
1150 32-plcc NH P4.3
DQ1
DQ2
VSS
DQ3
DQ4
DQ5 DQ5 DQ5
DQ1
DQ2
VSS
DQ3
DQ4
DQ1
DQ2
VSS
DQ3
DQ4
FIGURE 2: Pin Assignments for 32-lead PLCC
(c)2010 Silicon Storage Technology, Inc. S71150-14-000 01/10
4
DQ6
DQ6
DQ6
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512 A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1150 32-tsop WH P1.0
SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
Standard Pinout Top View Die Up
FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)
TOP VIEW (balls facing down) SST39LF/VF010 6 5 1150 48-tfbga B3K P2.0 A9 A8 A11 A12 NC A10 DQ6 DQ7 4 3 2 1 WE# NC NC NC DQ5 NC VDD DQ4 NC NC NC NC DQ2 DQ3 VDD NC A7 NC A6 A3 A4 A2 A5 DQ0 NC A1 NC DQ1 6 5 4 3 2 1
TOP VIEW (balls facing down) SST39LF/VF020
A14 A13 A15 A16 NC NC
NC VSS
A14 A13 A15 A16 A17 NC
NC VSS 1150 48-tfbga B3K P3.0
A9 A8 A11 A12 NC A10 DQ6 DQ7 WE# NC NC NC DQ5 NC VDD DQ4 NC NC NC NC DQ2 DQ3 VDD NC A7 NC A6 A3 A4 A2 A5 DQ0 NC A1 NC DQ1
A0 CE# OE# VSS
A0 CE# OE# VSS
A
B
C
D
E
F
G
H
A TOP VIEW (balls facing down) SST39LF/VF040
B
C
D
E
F
G
H
6 5 4 3 2 1
A14 A13 A15 A16 A17 NC
NC VSS 1150 48-tfbga B3K P4.0
A9 A8 A11 A12 NC A10 DQ6 DQ7 WE# NC NC NC DQ5 NC VDD DQ4 NC NC NC NC DQ2 DQ3 VDD NC A7 A18 A6 A3 A4 A2 A5 DQ0 NC A1 NC DQ1
A0 CE# OE# VSS
A
B
C
D
E
F
G
H
FIGURE 4: Pin Assignment for 48-ball TFBGA (6mm x 8mm) for 1 Mbit, 2 Mbit, and 4 Mbit
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
5
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TOP VIEW (balls facing down)
6
A2 A8 A17 A14 A9 A13 A11 NC1 OE# A10 CE#
5
A1 DQ7 DQ5 DQ6 DQ3 DQ4
1150 34-wfbga MM P5.0
4
A0 VDD WE# A16 A12 A18 A15 A6 A7 A5 A4 NC2 A3 A0 A2
3
CE# DQ2 VSS
2
VSS DQ0 DQ1 A1
1
A
B
C
D
E
F
G
H
J
Note: For SST39LF020, ball B3 is "No Connect" For SST39LF010, balls B3 and A5 are "No Connect"
FIGURE 5: Pin Assignment for 34-ball WFBGA (4mm x 6mm) for 1 Mbit and 2 Mbit TABLE 2: Pin Description
Symbol AMS1-A0 DQ7-DQ0 Pin Name Address Inputs Data Input/output Functions To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 3.0-3.6V for SST39LF512/010/020/040 2.7-3.6V for SST39VF512/010/020/040
CE# OE# WE# VDD VSS NC
Chip Enable Output Enable Write Enable Power Supply Ground No Connection
Unconnected pins.
T2.1 1150
1. AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
TABLE 3: Operation Modes Selection
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH See Table 4
T3.4 1150
CE# VIL VIL VIL VIH X X
OE# VIL VIH VIH X VIL X
WE# VIH VIL VIL X X VIH
DQ DOUT DIN X1 High Z High Z/ DOUT High Z/ DOUT
Address AIN AIN Sector address, XXH for Chip-Erase X X X
1. X can be VIL or VIH, but no other value.
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
6
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet TABLE 4: Software Command Sequence
Command Sequence Byte-Program Sector-Erase Chip-Erase Software ID Entry4,5 Software ID Exit6 Software ID Exit6 1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H XXH 5555H Data AAH AAH AAH AAH F0H AAH 2AAAH 55H 5555H F0H
T4.2 1150
2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH Data 55H 55H 55H 55H
3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H Data A0H 80H 80H 90H
4th Bus Write Cycle Addr1 BA2 5555H 5555H Data Data AAH AAH
5th Bus Write Cycle Addr1 2AAAH 2AAAH Data 55H 55H
6th Bus Write Cycle Addr1 SAX3 5555H Data 30H 10H
1. Address format A14-A0 (Hex), Address A15 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF512. Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence. AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 2. BA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A12 address lines 4. The device does not remain in Software Product ID mode if powered down. 5. With AMS-A1 = 0; SST Manufacturer's ID = BFH, is read with A0 = 0, SST39LF/VF512 Device ID = D4H, is read with A0 = 1, SST39LF/VF010 Device ID = D5H, is read with A0 = 1, SST39LF/VF020 Device ID = D6H, is read with A0 = 1, SST39LF/VF040 Device ID = D7H, is read with A0 = 1. 6. Both Software ID Exit operations are equivalent
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range for SST39LF512/010/020/040
Range Commercial Ambient Temp 0C to +70C VDD 3.0-3.6V
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load CL = 30 pF for SST39LF512/010/020/040 CL = 100 pF for SST39VF512/010/020/040 See Figures 15 and 16
Operating Range for SST39VF512/010/020/040
Range Commercial Industrial Ambient Temp 0C to +70C -40C to +85C VDD 2.7-3.6V 2.7-3.6V
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
7
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet TABLE 5: DC Operating Characteristics -VDD = 3.0-3.6V for SST39LF512/010/020/040 and 2.7-3.6V for SST39VF512/010/020/0401
Limits Symbol IDD Parameter Power Supply Current Read2 Program and Erase3 ISB ILI ILO VIL VIH VIHC VOL VOH Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 0.2 20 30 15 1 10 0.8 mA mA A A A V V V V V Min Max Units Test Conditions Address input=VILT/VIHT, at f=1/TRC Min VDD=VDD Max CE#=VIL, OE#=WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
T5.7 1150
1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25C (room temperature), and VDD = 3V for VF devices. Not 100% tested. 2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information. 3. 30 mA max for Erase operations in the industrial temperature range.
TABLE 6: Recommended System Power-up Timings
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Program/Erase Operation
Minimum 100 100
Units s s
T6.1 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: Capacitance (Ta = 25C, f=1 Mhz, other pins open)
Parameter CI/O
1
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 6 pF
T7.0 1150
CIN1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: Reliability Characteristics
Symbol NEND1,2 TDR1 ILTH1 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T8.3 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification.
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
8
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
AC CHARACTERISTICS
TABLE 9: Read Cycle Timing Parameters - VDD = 3.0-3.6V for SST39LF512/010/020/040 and 2.7-3.6V for SST39VF512/010/020/040
SST39LF512-45 SST39LF010-45 SST39LF020-45 SST39LF040-45 Symbol Parameter TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ TOH1
1
SST39LF020-55 SST39LF040-55 Min 55 Max 55 55 30 0 0
SST39VF512-70 SST39VF010-70 SST39VF020-70 SST39VF040-70 Min 70 70 70 35 0 0 Max Units ns ns ns ns ns ns 25 25 0 ns ns ns
T9.2 1150
Min 45
Max 45 45 30
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output
Output Hold from Address Change
0 0 15 15 0
15 15 0
TOHZ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: Program/Erase Cycle Timing Parameters
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH1 TDS TDH1 TIDA TSE TSCE
1
Parameter Byte-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Chip-Erase
Min 0 30 0 0 0 10 40 40 30 30 40 0
Max 20
Units s ns ns ns ns ns ns ns ns ns ns ns ns
150 25 100
ns ms ms
T10.1 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
9
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TRC ADDRESS AMS-0 TCE CE# TOE OE# VIH WE# TCLZ DQ7-0 Note: HIGH-Z TOLZ
TAA
TOHZ
TOH DATA VALID
TCHZ DATA VALID HIGH-Z
AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
1150 F03.0
FIGURE 6: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TWP WE# TAS OE# TCH CE# TCS DQ7-0 AA SW0 Note: 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA)
1150 F04.0
2AAA
5555
ADDR TDH
TWPH
TDS
AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 7: WE# Controlled Program Cycle Timing Diagram
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
10
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TCP CE# TAS OE# TCH WE# TCS DQ7-0 AA SW0 Note: 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TCPH TDS 2AAA 5555 ADDR TDH
1150 F05.0
AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 8: CE# Controlled Program Cycle Timing Diagram
ADDRESS AMS-0 TCE CE# TOEH OE# TOE WE# TOES
DQ7 Note:
D
D#
D#
D
1150 F06.0
AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
FIGURE 9: Data# Polling Timing Diagram
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
11
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
ADDRESS AMS-0 TCE CE# TOEH OE# TOE TOES
WE#
DQ6
TWO READ CYCLES
Note:
WITH SAME OUTPUTS AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040
1150 F07.0
FIGURE 10: Toggle Bit Timing Diagram
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX
TSE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
30 SW5
1150 F08.0
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
FIGURE 11: WE# Controlled Sector-Erase Timing Diagram
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
12
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
1150 F17.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
FIGURE 12: WE# Controlled Chip-Erase Timing Diagram
Three-byte Sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
CE#
OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2 TAA BF Device ID
1150 F09.2
TIDA
Note: Device ID = D4H for SST39LF/VF512, D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040.
FIGURE 13: Software ID Entry and Read
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
13
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
AA
55
F0 TIDA
CE#
OE# TWP WE# TWHP SW0 SW1 SW2
1150 F10.0
FIGURE 14: Software ID Exit and Reset
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1150 F12.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 15: AC Input/Output Reference Waveforms
TO TESTER
TO DUT CL
1150 F11.1
FIGURE 16: A Test Load Example
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
14
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Start
Load data: AAH Address: 5555H
Load data: 55H Address: 2AAAH
Load data: A0H Address: 5555H
Load Byte Address/Byte Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
1150 F13.1
FIGURE 17: Byte-Program Algorithm
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
15
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Internal Timer Byte-Program/ Erase Initiated
Toggle Bit Byte-Program/ Erase Initiated
Data# Polling Byte-Program/ Erase Initiated
Wait TBP, TSCE, or TSE
Read byte
Read DQ7
Program/Erase Completed
Read same byte
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes
Program/Erase Completed
Program/Erase Completed
1150 F14.0
FIGURE 18: Wait Options
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
16
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Software ID Entry Command Sequence
Software ID Exit & Reset Command Sequence
Load data: AAH Address: 5555H
Load data: AAH Address: 5555H
Load data: F0H Address: XXH
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Wait TIDA
Load data: 90H Address: 5555H
Load data: F0H Address: 5555H
Return to normal operation
Wait TIDA
Wait TIDA
Read Software ID
Return to normal operation
1150 F15.2
FIGURE 19: Software ID Command Flowcharts
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
17
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Chip-Erase Command Sequence Load data: AAH Address: 5555H
Sector-Erase Command Sequence Load data: AAH Address: 5555H
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Load data: 80H Address: 5555H
Load data: 80H Address: 5555H
Load data: AAH Address: 5555H
Load data: AAH Address: 5555H
Load data: 55H Address: 2AAAH
Load data: 55H Address: 2AAAH
Load data: 10H Address: 5555H
Load data: 30H Address: SAX
Wait TSCE
Wait TSE
Chip erased to FFH
Sector erased to FFH
1150 F16.1
FIGURE 20: Erase Command Sequence
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
18
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
PRODUCT ORDERING INFORMATION
SST 39 XX LF 040 XX XXXX - 45 - XXX 4C XX NH - XXX E X Environmental Attribute E1 = non-Pb Package Modifier H = 32 leads K = 48 balls M = 34 balls (54 possible positions) Package Type B3 = TFBGA (0.8mm pitch, 6mm x 8mm) N = PLCC M = WFBGA (0.5mm pitch, 4mm x 6mm) W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 45 = 45 ns 55 = 55 ns 70 = 70 ns Device Density 040 = 4 Mbit 020 = 2 Mbit 010 = 1 Mbit 512 = 512 Kbit Voltage L = 3.0-3.6V V = 2.7-3.6V Product Series 39 = Multi-Purpose Flash
1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are RoHS compliant.
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
19
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet Valid combinations for SST39LF512 SST39LF512-45-4C-NHE SST39LF512-45-4C-WHE
Valid combinations for SST39VF512 SST39VF512-70-4C-NHE SST39VF512-70-4I-NHE SST39VF512-70-4C-WHE SST39VF512-70-4I-WHE
Valid combinations for SST39LF010 SST39LF010-45-4C-NHE SST39LF010-45-4C-WHE SST39LF010-45-4C-B3KE SST39LF010-45-4C-MME
Valid combinations for SST39VF010 SST39VF010-70-4C-NHE SST39VF010-70-4I-NHE SST39VF010-70-4C-WHE SST39VF010-70-4I-WHE SST39VF010-70-4C-B3KE SST39VF010-70-4I-B3KE
Valid combinations for SST39LF020 SST39LF020-45-4C-NHE SST39LF020-55-4C-NHE SST39LF020-45-4C-WHE SST39LF020-55-4C-WHE SST39LF020-45-4C-B3KE SST39LF020-45-4C-MME
Valid combinations for SST39VF020 SST39VF020-70-4C-NHE SST39VF020-70-4I-NHE SST39VF020-70-4C-WHE SST39VF020-70-4I-WHE SST39VF020-70-4C-B3KE SST39VF020-70-4I-B3KE
Valid combinations for SST39LF040 SST39LF040-45-4C-NHE SST39LF040-55-4C-NHE SST39LF040-45-4C-WHE SST39LF040-55-4C-WHE SST39LF040-45-4C-B3KE
Valid combinations for SST39VF040 SST39VF040-70-4C-NHE SST39VF040-70-4I-NHE SST39VF040-70-4C-WHE SST39VF040-70-4I-WHE SST39VF040-70-4C-B3KE SST39VF040-70-4I-B3KE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
20
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
Optional Pin #1 Identifier .048 .042 .495 .485 .453 .447
2 1 32
SIDE VIEW
.112 .106 .020 R. MAX. .029 x 30 .023 .040 R. .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 BSC .490
.050 BSC .015 Min. .050 BSC .095 .075 .140 .125 .032 .026
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils.
32-plcc-NH-3
FIGURE 21: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH
TOP VIEW
8.00 0.20
BOTTOM VIEW
5.60 0.80 0.45 0.05 (48X)
6 5 4 3 2 1
0.80 ABCDEFGH A1 CORNER HGFEDCBA 4.00 6.00 0.20
6 5 4 3 2 1
SIDE VIEW
1.10 0.10
A1 CORNER
SEATING PLANE 0.35 0.05
0.12
1mm
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-tfbga-B3K-6x8-450mic-4
FIGURE 22: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm SST Package Code: B3K
(c)2010 Silicon Storage Technology, Inc. S71150-14-000 01/10
21
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Pin # 1 Identifier
1.05 0.95 0.50 BSC
8.10 7.90
0.27 0.17
12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80
0.15 0.05
0- 5 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
32-tsop-WH-7
FIGURE 23: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
22
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TOP VIEW
6.00 0.08
BOTTOM VIEW
4.00 0.50 0.32 0.05 (34X)
6 5 4 3 2 1 JHGFEDCBA
6 5 4 3 2 1 ABCDEFGHJ
4.00 0.08
2.50
0.50
A1 CORNER
A1 INDICATOR4
0.63 0.10
DETAIL
SIDE VIEW
0.08
SEATING PLANE
0.20 0.06
1mm
Note:
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.08 mm 4. No ball is present in position A1; a gold-colored indicator is present. 34-wfbga-MM-4x6-32mic-1 5. Ball opening size is 0.29 mm ( 0.05 mm)
FIGURE 24: 34-ball Very-very-thin-profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm x .63mm SST Package Code: MM
(c)2010 Silicon Storage Technology, Inc.
S71150-14-000
01/10
23
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet TABLE 11: Revision History
Number 01 02 03 04 Description Date Feb 2000 Aug 2000 Oct 2002
* * * * * *
2000 Data Book Changed speed from 45 ns to 55 ns for the SST39LF020 and SST39LF040 Added the B3K package for the 2 Mbit devices Added footnote in Table 5 to indicate IDD Write is 30 mA max for Erase operations in the Industrial temperature range.
2002 Data Book: Reintroduced the 45 ns parts for the SST39LF020 and SST39LF040 Feb 2002
05
Changes to Table 5 on page 8 - Added footnote for MPF power usage and Typical conditions - Clarified the Test Conditions for Power Supply Current and Read parameters - Clarified IDD Write to be Program and Erase - Corrected IDD Program and Erase from 20 mA to 30 mA * Part number changes - see page 20 for additional information Added new "MM" Micro-Package MPNs for 1M and 2M LF parts- see page 20 2004 Data Book Added non-Pb MPNs and removed footnote (See page 20) Updated B3K and MM package diagrams Added RoHS Compliant statement. Added 4 MBit to Figure 4. Revised Absolute Max Stress Ratings for Surface Mount Solder Reflow Temperature Removed SST39VFxxx-90 Timing Parameters from Figure 9. Added Footnote and removed Read Access Speed 90 = 90 to Product Ordering Information. Removed 90 part numbers Valid Combinations lists Edited page Valid Combinations on page 21. Changed 39LF040-70-4C-B3KE to 39LF040-45-4C-B3KE Removed leaded parts Added package YME Revised "Product Ordering Information" on page 19 Changed endurance from 10,000 to 100,000 in Product Description, page 1 EOL of SST39LF010-45-4C-YME. Replacement part is SST39LF010-45-4C-MME in this document. Removed all references to the YME package.
Mar 2003
06 07
* * * * * * * * * *
Oct 2003 Nov 2003
08
Dec 2005
09 10 11 12 13 14
* * * * * * *
Jan 2006 Nov 2008 Feb 2009 Apr 2009 Sep 2009 Jan 2010
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2010 Silicon Storage Technology, Inc. S71150-14-000 01/10
24

▲Up To Search▲

Price & Availability of SST39LF010-45-4C-B3HE

	To Download SST39LF010-45-4C-B3HE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .